VLSI Interview Questions for Freshers and Experienced | VLSI Interview Questions And Answers (Expected) | VLSI ECE/EEE VIVA FAQ's
The below VLSI questions are expected in interviews for both freshers and experienced candidates seeking for a job in circuit designing companies. We have collected 50 most expected and frequently asked VLSI interview questions. The questions are from basic level to advanced level.
VLSI VIVA Interview Questions |
VLSI Interview Questions for Freshers
- What are Integration Circuits?
- What are the differences between SSI, LSI, MSI, and VLSI?
- What are Application Specific Integration Circuits(ASIC)?
- What are the types of transistors in CMOS?
- What are the advantages of using CMOS process?
- Define threshold voltage in CMOS?
- What are the techniques to minimize the power consumption in CMOS logic?
- What is the difference between n-type transistors and p-type transistors?
- What is Enhancement mode transistor?
- What are the steps involved in twin tub process?
- What is Bipolar Complementary Metal Oxide Semiconductor (BICMOS)?
- What is a pulldown device?
- What is Noise Margin?
- What are the different operating regions for a MOS transistor?
- What the color coding represents in stick diagram?
- What is Body Effect?
- What is Latch-up?
- What is Verilog?
- Why NAND gate is preferred over NOR gate in fabrication?
- What happens to delay if you improve load capacitance?
- Why is the substrate in NMOS connected to Ground and in PMOS to Vdd?
- Why PMOS and NMOS are sized equally in transmission gates?
- What happens to delay If you include a resistor at the output of the CMOS circuit?
- Explain Gate level modeling, data flow modeling, switch level modeling, and behavioral modeling?
- Why do we gradually increase the size of inverters in buffer design?
- What are identifiers?
- What is electron scattering?
- Draw various symbols of the transmission gate?
- What is the full custom ASIC design?
- What is Field Programmable Gate Array(FPGA)?
- What are macros?
- What is Interface Design Document Test(IDD test)?
- What is metastability and when does it occur?
- What are the different ways to reduce metastable state?
- Differentiate parallel simulation and concurrent simulation?
- What is ad-hoc testing?
- What is BILBO(Built-In Logic Block Observer)?
- Explain the sizing of inverters?
- What is IDDQ (Indefinite Delivery Definite Quantity) testing?
- What is a boundary scan?
- What happens when PMOS and NMOS are interchanged in a CMOS inverter?
- How the dynamic gate works?
- What are the advantages and disadvantages of synchronous and asynchronous resets?
- How does the Fanout concept help CMOS gates?
- What are the different type of Adder circuits you know?
- How the Binary Counter works?
- How many transistors are required in CMOS to implement a NAND Gate?
- What is the use of a tri-state bus?
- What is the difference between latches and flip-flops based designs?
- What type of measures are needed to reduce the manufacturing flaws?
1 comment:
A collection of VLSI/ASIC logic design interview questions, partially documented at really taken interviews, partially designed based on the commonly asked questions and usually touched issues is at https://vlsiquestions.wixsite.com/vlsiquestions.
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